M3: panel renders — TC358762 bridge init + non-burst DSI

The Hosyond 5" panel uses Pi 7" v1.1 architecture (ATTINY ID 0xC3 +
TC358762 DSI-to-DPI bridge). Getting it to paint needed three things
that ESP-IDF doesn't expose:

  1. TC358762 bridge configuration — 16 register writes via DSI Generic
     Long Write (DT=0x29) packets, transcribed from Linux's tc358762.c.
  2. Non-burst video mode — IDF hardcodes BURST_WITH_SYNC_PULSES, but
     TC358762 requires NON_BURST_WITH_SYNC_PULSES. Overridden via the
     mipi_dsi_host_ll_* API after esp_lcd_new_panel_dpi() and before
     panel_init().
  3. ATTINY v1.1 power-on sequence + SPI-proxy bridge wake. The legacy
     REG_POWERON(0x85) path doesn't apply to 0xC3 firmware; instead
     write PORTC/PORTA/PORTB/PORTC in order, then later release bridge
     reset and proxy-write TC358762 SYSPMCTRL=0 through the ATTINY's
     ADDR_H/L + WR_DATA_H/L registers.

Reaching the LL/HAL APIs requires shadowing esp_lcd_dsi_bus_t so we can
pick the mipi_dsi_hal_context_t out of the private struct. Documented
the layout dependency at the shadow definition.

Tuned config (observed stable on ESP32-P4 per embenix's reference):
  - 1 data lane @ 600 Mbps
  - DPI 26 MHz (Linux modeline is 25.98)
  - timings HSW=2 HBP=46 HFP=210 / VSW=20 VBP=4 VFP=22
  - RGB888 end-to-end, R,G,B byte order (BGR was wrong)
  - disable_lp=0 so LP windows are available for the bridge writes

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